Editing Universal Superposition of Orthogonal States (section)

==Outline==
Superposition of arbitrary orthogonal states can be generated with two different types of outputs according to functionality and the desired probability of success. In the first case, a superposition of the two arbitrary states is generated as a pure state with a maximum probability (but not equal to unity) of success. The output state has the well-defined form of the superposition with the desired absolute value and a relative sign of the superposition. In the second case, mixed output state, a superposition with the desired form is successfully generated in all the rounds and thus the success probability of the protocol is equal to one. In this recent case, a mixed state is generated which is the combination of all pure superposed states with different superposition signs and relative phases.
[[File:Universal Superposition.png|right|thumb|1000px|The quantum circuit presentation of the protocol]]
*'''Pure Output Case:''' First, an [[ancillary]] qubit in standard basis must be prepared with the desired weights of the final superposition. Then the [[quantum adder]] circuit must be operated on the two arbitrary and this ancilary qubit. The circuit's gates are as follows: A [[controlled swap gate]] acting on input qubits and its control qubit is the ancillary qubit. Then a CNOT gate (controlled X gate) is performed on the first input qubit with the same control qubit. The next step is the measurement. The ancillary qubit is measured in the X basis and the first input state is measured in the Z basis. If the output of the X measurement is the state with positive eigenvalue (or plus state) and the result of the Z measurement is the state with negative eigenvalue (the 1 state) the protocol is successful and the output is the superposition of the two input states with the desired weights. Otherwise, the round should be ignored.
* '''Mixed Output Case:''' In the second case, the circuit is the same as for the pure output case. The only difference is that at the measurement step, regardless of the outcome of the measurements, we will not ignore any rounds and all the outcome states are valid superposition but they differ by a relative phase with each other (with negative or positive sign). As a result, the output of the circuit will be always a desired superposed state. In the cases which the relative phase of the superposition can be ignored, this case can be considered as a deterministic protocol.